The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Mar. 26, 2017
Applicant:

Nxp Usa, Inc., Austin, TX (US);

Inventors:

Luv Pandey, Noida, IN (US);

Sanjoy Kumar Dey, Noida, IN (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/38 (2006.01); H03M 1/00 (2006.01); H03K 17/16 (2006.01);
U.S. Cl.
CPC ...
H03M 1/002 (2013.01); H03K 17/161 (2013.01); H03M 1/38 (2013.01);
Abstract

In an analog-to-digital converter (ADC) having storage capacitors, passive top-plate switch circuitry has at least one diode-configured transistor connected between a first transistor and the top-plate node of the storage capacitors to provide a diode-voltage drop that ensures that the voltage at the node between two transistors is different from the top-plate node voltage in order to reduce GIDL/GISL leakage current through the first transistor that could adversely affect the ADC's digital output value. A corresponding capacitor is connected across each diode-configured device to reduce the amount of charge needed to achieve intermediate-node, steady-state voltages when the switch circuitry is off. In an n-type implementation, a reverse-diode-biased isolation device is connected between the top-plate node and the at least one diode-configured device to prevent the top-plate node from seeing the large dynamic junction capacitance of the at least one diode-configured device.


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