The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2017
Filed:
Jan. 13, 2016
Applicant:
Xinnova Technology Limited, Beijing, CN;
Inventors:
Assignee:
XINNOVA TECHNOLOGY LIMITED, Beijing, CN;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 21/265 (2006.01); H01L 21/28 (2006.01); H01L 27/11521 (2017.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/02 (2006.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
H01L 29/7883 (2013.01); H01L 21/26513 (2013.01); H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 29/401 (2013.01); H01L 29/42328 (2013.01); H01L 29/66825 (2013.01); H01L 21/02238 (2013.01); H01L 27/11524 (2013.01);
Abstract
A non-volatile memory unit and method of manufacturing the same are disclosed. The non-volatile memory unit includes a substrate with a source region and a drain region. A first dielectric layer forms on the substrate. An erase gate, a floating gate and couple control gate are forms on the first dielectric layer. The second dielectric layer and coupled dielectric layer are formed among and above the erase gate, the floating gate and the selective gate, and formed on the couple control gate of the coupled dielectric layer.