The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2017
Filed:
Dec. 11, 2015
Jae-yup Chung, Yongin-si, KR;
Yoon-seok Lee, Seoul, KR;
Hyun-jo Kim, Seoul, KR;
Hwa-sung Rhee, Seongnam-si, KR;
Hee-don Jeong, Hwaseong-si, KR;
Se-wan Park, Seoul, KR;
Bo-cheol Jeong, Suwon-si, KR;
Jae-yup Chung, Yongin-si, KR;
Yoon-seok Lee, Seoul, KR;
Hyun-jo Kim, Seoul, KR;
Hwa-sung Rhee, Seongnam-si, KR;
Hee-don Jeong, Hwaseong-si, KR;
Se-wan Park, Seoul, KR;
Bo-cheol Jeong, Suwon-si, KR;
Abstract
An integrated circuit device includes first and second fin-type active regions having different conductive type channel regions, a first device isolation layer covering both sidewalk of the first fin-type active region, and a second device isolation layer covering both sidewalls of the second fin-type active region. The first device isolation layer and the second device isolation layer have different stack structures. To manufacture the integrated circuit device, the first device isolation layer covering both sidewalls of the first fin-type active region and the second device isolation layer covering both sidewalk of the second fin-type active region are formed after the first fin-type active region and the second fin-type active region are formed. The first device isolation layer and the second device isolation layer are formed to have different stack structure.