The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Jul. 24, 2015
Applicant:

Altera Corporation, San Jose, CA (US);

Inventors:

Zhe Li, San Jose, CA (US);

Yuanlin Xie, Fremont, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 21/56 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0655 (2013.01); H01L 21/565 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/3107 (2013.01); H01L 23/49816 (2013.01); H01L 23/528 (2013.01); H01L 23/5223 (2013.01); H01L 23/5226 (2013.01); H01L 23/5227 (2013.01); H01L 24/89 (2013.01); H01L 25/50 (2013.01); H01L 2224/08225 (2013.01); H01L 2224/80001 (2013.01); H01L 2924/1205 (2013.01); H01L 2924/1206 (2013.01); H01L 2924/14 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01);
Abstract

An integrated circuit package with embedded passive structures may include first and second integrated circuit dies that are surrounded by capacitor structures. A molding compound is deposited to encapsulate the integrated circuit dies and the capacitor structures. The molding compound is then attached to a redistribution wafer, in which the integrated circuit dies and the capacitor structures are electrically connected to metal routing layers of the redistribution wafer. A conductive layer is subsequently formed over the first integrated circuit die in the molding compound. The conductive layer is made up of additional metal routing layers and inductor structures. The integrated circuit package may further include a group of conductive vias that is formed in the molding compound. Each conductive via has a first end contacting the metal routing layers of the distribution wafer, and a second end contacting the conductive layer.


Find Patent Forward Citations

Li, Zhe. (2017). Integrated circuit package with embedded passive structures (U.S. Patent No. 9673173). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9673173

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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