The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Nov. 30, 2016
Applicant:

Integrated Silicon Solution, Inc., Milpitas, CA (US);

Inventor:

Kyoung Chon Jin, San Ramon, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/04 (2006.01); G11C 16/34 (2006.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); H01L 23/528 (2006.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
G11C 16/10 (2013.01); G11C 16/0425 (2013.01); G11C 16/0483 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/345 (2013.01); G11C 16/3459 (2013.01); H01L 23/528 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 29/7884 (2013.01);
Abstract

A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.


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