Operation modes for an inverted nand architecture

Abstract

Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.