The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Aug. 25, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Anirban Roy, Austin, TX (US);

Michael A. Sadd, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 14/00 (2006.01); G11C 5/06 (2006.01); G11C 13/00 (2006.01); G11C 11/419 (2006.01); G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
G11C 14/009 (2013.01); G11C 5/06 (2013.01); G11C 11/419 (2013.01); G11C 13/004 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); G11C 11/005 (2013.01);
Abstract

A memory device includes a volatile memory cell and a non-volatile memory cell. The non-volatile memory cell includes a first resistive element having a first terminal and a second terminal and a second resistive element having a first terminal and a second terminal. The first terminal of the first resistive element is coupled to the first terminal of the second resistive element at a first node. The second terminal of the first resistive element is coupled to a first source line voltage. The second terminal of the second resistive element is coupled to a second source line voltage. A first transistor includes a first current electrode coupled to a first data storage node of the volatile memory cell, a second current electrode coupled to a supply voltage, and a control gate coupled to the first node.


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