The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Dec. 21, 2011
Applicants:

Yunbiao Ben Lin, ShangHai, CN;

Jianghong Julie Du, ShangHai, CN;

Inventors:

Yunbiao Ben Lin, ShangHai, CN;

Jianghong Julie Du, ShangHai, CN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06T 1/60 (2006.01); G06F 12/1027 (2016.01); G06F 9/455 (2006.01); G09G 5/36 (2006.01); G09G 5/39 (2006.01);
U.S. Cl.
CPC ...
G06T 1/60 (2013.01); G06F 9/45533 (2013.01); G06F 12/1027 (2013.01); G09G 5/363 (2013.01); G09G 5/39 (2013.01);
Abstract

In accordance with embodiments disclosed herein, there are provided methods, systems, mechanisms, techniques, and apparatuses for implementing GPU (Graphics Processing Unit) accelerated address translation for graphics virtualization. In one embodiment, such a system includes a main memory having a plurality of machine physical addresses; a graphics processor unit having graphics memory therein; an address translation service integrated with the graphics processor unit; a hypervisor to manage one or more guest machines; wherein the hypervisor is to configure a lookup table within the graphics memory of the graphics processor unit; and further wherein the address translation service of the graphics processor unit is to translate a guest physical address for one of the one or more guest machines to a corresponding machine physical address within the main memory. Such a graphics processor unit may be implemented separate from a system, for example, embodied within a silicon integrated circuit.


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