The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 06, 2017
Filed:
Sep. 15, 2014
Applicant:
Microsemi Soc Corporation, San Jose, CA (US);
Inventor:
G. Richard Newell, Tracy, CA (US);
Assignee:
Microsemi SoC Corporation, San Jose, CA (US);
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 29/06 (2006.01); G06F 21/76 (2013.01); H04L 9/32 (2006.01); H04L 9/08 (2006.01); G06F 21/12 (2013.01); G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 21/76 (2013.01); H04L 9/0877 (2013.01); H04L 9/3226 (2013.01); H04L 9/3234 (2013.01); H04L 9/3263 (2013.01); G06F 17/5054 (2013.01); G06F 21/125 (2013.01);
Abstract
A method for securely programming a population of authorized FPGAs includes defining the population of authorized FPGAs, generating an encrypted configuration bitstream for the population of authorized FPGAs, generating an individual Authorization Code for each FPGA in the population of authorized FPGAs, feeding the individual Authorization Codes into the FPGAs in the population of FPGAs, feeding the encrypted configuration bitstream into all of the FPGAs in the population of FPGAs, and in each FPGA using the Authorization Code to decrypt the encrypted configuration bitstream to program the FPGA.