Method for gating clock signals using late arriving enable signals

Abstract

A method for designing clock gates which may reduce timing requirements associated with clock gating control signals may include identifying a clock gating function included in a Hardware Description Language of an integrated circuit, wherein the clock gating function may include capturing a state of an enable signal dependent upon a clock signal. The method may include determining a delay time for capturing the state of the enable signal dependent on a time difference between transitions of the enable signal and the clock signal. The method may include creating a gating circuit, in which the gating circuit includes a delay unit coupled to a source of the clock signal, and wherein a delay value is dependent upon the amount of time to delay capturing the enable signal. The method may include modifying the HDL model dependent upon the clock gating circuit.