The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Jun. 25, 2014
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Akira Goda, Boise, ID (US);

Pranav Kalavade, San Jose, CA (US);

Charan Srinivasan, Redwood City, CA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1068 (2013.01);
Abstract

Technology for programming a page of memory in a NAND memory device is disclosed and described. In an example, a method includes applying initial programming pulses for lower page programming of the page and pre-reading data of the lower page. The method also includes determining whether to apply an error recovery operation to the data of the lower page. Data indicative of secondary programming pulses to be used for programming upper page data are stored and the upper page data is programmed based on the secondary programming pulses and the data of the lower page.


Find Patent Forward Citations

Goda, Akira. (2017). Nand memory devices systems, and methods using pre-read error recovery protocols of upper and lower pages (U.S. Patent No. 9672102). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9672102

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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