The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 2017

Filed:

Apr. 23, 2012
Applicants:

Yoav Weizman, Kfar-Vitkin, IL;

Jacob Fridburg, Gan Yavne, IL;

Shai Shperber, Bat Hefer, IL;

Inventors:

Yoav Weizman, Kfar-Vitkin, IL;

Jacob Fridburg, Gan Yavne, IL;

Shai Shperber, Bat Hefer, IL;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G01R 31/317 (2006.01); G01R 31/308 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2882 (2013.01); G01R 31/308 (2013.01); G01R 31/31725 (2013.01); H01L 22/12 (2013.01); H01L 22/20 (2013.01); H01L 22/34 (2013.01);
Abstract

A semiconductor device arrangement comprising a functional circuit comprising a plurality of timing components and a reference module comprising a plurality of reference components is described. Each reference component comprises a reference timing component corresponding to a timing component of the plurality of timing components and a controllable timing component. The controllable timing component is arranged to provide a delay in dependence on an applied light stimulus. A method of analyzing a performance of a functional circuit on a semiconductor device is also described. A device analysis system for analyzing a functional circuit comprising a plurality of timing components is also described.


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