The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2017
Filed:
Mar. 09, 2016
Microsemi Semiconductor Ulc, Kanata, CA;
Qu Gary Jin, Kanata, CA;
Paul H. L. M. Schram, Bergen op zoom, NL;
Krste Mitric, Ottawa, CA;
Cathy Zhang, Ottawa, CA;
Gabriel Rusaneanu, Ottawa, CA;
Wenbao Wang, Kanata, CA;
MICROSEMI SEMICONDUCTOR ULC, Kanata, Ontario, CA;
Abstract
In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.