The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

May. 09, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Chih-Hao Wang, Hsinchu County, TW;

Ching-Wei Tsai, Hsinchu, TW;

Chin-Chi Wang, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/762 (2006.01); H01L 29/06 (2006.01); H01L 21/8238 (2006.01); H01L 21/84 (2006.01); H01L 27/092 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 21/76224 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 21/823878 (2013.01); H01L 21/845 (2013.01); H01L 27/0924 (2013.01); H01L 29/0649 (2013.01); H01L 29/0653 (2013.01); H01L 29/6681 (2013.01);
Abstract

A device includes a first fin including a first semiconductor material. A first dielectric layer is disposed over a top surface of the first fin. A sidewall of the first dielectric layer has a dip-shape profile. A second dielectric layer is disposed along sidewalls of the first fin. A top surface of the second dielectric layer is substantially coplanar with the top surface of the first fin. A second fin includes a second semiconductor material different from the first semiconductor material. An isolation region is disposed between the first fin and the second fin.


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Wang, Chih-Hao. (2017). Finfet device (U.S. Patent No. 9666672). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9666672

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