The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2017
Filed:
Sep. 25, 2015
Applicant:
Kabushiki Kaisha Toshiba, Minato-ku, JP;
Inventors:
Assignee:
KABUSHIKI KAISHA TOSHIBA, Minato-ku, JP;
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 27/11582 (2017.01); H01L 27/11578 (2017.01); H01L 27/11551 (2017.01); H01L 27/11514 (2017.01); H01L 27/11575 (2017.01); H01L 27/11556 (2017.01); H01L 21/28 (2006.01); H01L 27/11548 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/28282 (2013.01); H01L 27/11514 (2013.01); H01L 27/11551 (2013.01); H01L 27/11575 (2013.01); H01L 27/11578 (2013.01); H01L 21/28273 (2013.01); H01L 27/11548 (2013.01); H01L 27/11556 (2013.01); H01L 2924/1438 (2013.01);
Abstract
A semiconductor memory device includes a first layer, a plurality of memory areas, a plurality of contact wires, a first shunt wire, and a second shunt wire. The memory areas are provided on the first layer in a first direction. The contact wires have a longitudinal direction in a second direction perpendicular to the first layer. The contact wires are provided between the adjacent memory areas on the first layer in a third direction intersecting the first direction. The first shunt wire commonly connects the contact wires. The second shunt wire extends in the first direction and is electrically connected to the first shunt wire.