The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Apr. 28, 2016
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Manfred Schneegans, Vaterstetten, DE;

Bernhard Weidgans, Bernhardswald, DE;

Franziska Haering, Regensburg, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/4763 (2006.01); H01L 23/00 (2006.01); H01L 21/027 (2006.01); H01L 23/31 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 24/06 (2013.01); H01L 21/0273 (2013.01); H01L 21/76864 (2013.01); H01L 21/76865 (2013.01); H01L 23/3157 (2013.01); H01L 24/03 (2013.01); H01L 2224/05147 (2013.01); H01L 2924/1306 (2013.01);
Abstract

A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in a second region. The method further includes depositing a first conductive material within first openings within a resist layer formed over the conductive liner. The first conductive material overfills to form a first pad and a first layer of a second pad. The method further includes depositing a second resist layer over the first conductive material, and patterning the second resist layer to form second openings exposing the first layer of the second pad without exposing the first pad. A second conductive material is deposited over the second layer of the second pad.


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