The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

May. 12, 2015
Applicant:

Fairchild Korea Semiconductor Ltd., Gyeonggi-do, KR;

Inventors:

Seung-won Im, Gyeonggi-do, KR;

O-seob Jeon, Seoul, KR;

Joon-seo Son, Seoul, KR;

Assignee:

Fairchild Korea Semiconductor, Ltd., Bucheon-si, Geonggi-Do, KR;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 23/495 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2006.01); H01L 25/16 (2006.01); H01L 23/373 (2006.01); H01L 23/433 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49575 (2013.01); H01L 23/3735 (2013.01); H01L 23/4334 (2013.01); H01L 23/49503 (2013.01); H01L 23/49558 (2013.01); H01L 23/49562 (2013.01); H01L 24/49 (2013.01); H01L 25/072 (2013.01); H01L 25/16 (2013.01); H01L 25/18 (2013.01); H01L 24/45 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/45124 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48095 (2013.01); H01L 2224/48101 (2013.01); H01L 2224/48137 (2013.01); H01L 2224/48139 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49111 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/73265 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1426 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor package with a leadframe to mount a transistor device prevents malfunction. The semiconductor package includes a leadframe including at least one or more transistor die attach pads where a first transistor device and a second transistor device are arranged, a driver die attach pad where a driver semiconductor chip is arranged, a first driver lead electrically connected to the driver semiconductor chip, and a second driver lead arranged between the first driver lead and the at least one or more transistor die attach pads, a chip bonding wire electrically connecting the first transistor device with the driver semiconductor chip, a first transistor bonding wire electrically connecting the first driver lead with the second transistor device, and a first insulator arranged on the second driver lead to insulate the second driver lead and the first transistor bonding wire from each other.


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