The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2017
Filed:
May. 20, 2016
Applicant:
United Microelectronics Corp., Hsinchu, TW;
Inventor:
Ching-Hung Kao, Hsinchu County, TW;
Assignee:
UNITED MICROELECTRONICS CORP., Hsinchu, TW;
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/761 (2006.01); H01L 21/762 (2006.01); H01L 27/146 (2006.01); H01L 21/306 (2006.01); H01L 21/308 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76224 (2013.01); H01L 21/3083 (2013.01); H01L 21/3085 (2013.01); H01L 21/30604 (2013.01); H01L 21/76237 (2013.01); H01L 27/1463 (2013.01); H01L 27/14689 (2013.01); H01L 29/0649 (2013.01); H01L 29/66553 (2013.01);
Abstract
A semiconductor device and a manufacturing method thereof are disclosed. The semiconductor device includes a silicon substrate, a spacer, a doped region, and a deep trench isolation (DTI). The silicon substrate has a deep trench. The spacer is formed on an upper portion of the sidewall of the deep trench. The doped region is formed on a lower portion of the sidewall of the deep trench. The deep trench isolation is formed in the deep trench.