The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2017
Filed:
Jun. 26, 2016
Applicant:
Ememory Technology Inc., Hsin-Chu, TW;
Inventors:
Assignee:
eMemory Technology Inc., Hsin-Chu, TW;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 27/115 (2017.01); H01L 29/788 (2006.01); H01L 27/11558 (2017.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/792 (2006.01); H01L 27/1157 (2017.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); H01L 27/11524 (2017.01); G11C 16/34 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0433 (2013.01); G11C 16/0416 (2013.01); G11C 16/0441 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11558 (2013.01); H01L 29/0649 (2013.01); H01L 29/42328 (2013.01); H01L 29/42344 (2013.01); H01L 29/45 (2013.01); H01L 29/512 (2013.01); H01L 29/66545 (2013.01); H01L 29/66833 (2013.01); H01L 29/788 (2013.01); H01L 29/7881 (2013.01); H01L 29/7882 (2013.01); H01L 29/792 (2013.01); G11C 2216/10 (2013.01);
Abstract
A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.