The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2017
Filed:
Dec. 08, 2014
Applicant:
Texas Instruments Incorporated, Dallas, TX (US);
Inventors:
Ashesh Parikh, Frisco, TX (US);
Chi-Chien Ho, Plano, TX (US);
Thomas John Smelko, Richardson, TX (US);
Rajni J. Aggarwal, Garland, TX (US);
Assignee:
TEXAS INSTRUMENTS INCORPORATED, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 21/8234 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
G06F 17/5045 (2013.01); G06F 17/5063 (2013.01); G06F 17/5068 (2013.01); H01L 21/823456 (2013.01); H01L 22/34 (2013.01); G06F 2217/12 (2013.01); H01L 22/20 (2013.01); Y02P 90/265 (2015.11);
Abstract
A method to adjust transistor gate geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to form a reticle. A method to adjust transistor geometries in a design data base to compensate for transistor-to-transistor active overlap of gate differences and to compensate for transistor turn on voltage drop off where the transistor gate crosses the isolation/active interface.