The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Sep. 24, 2014
Applicants:

Sanjay R. Deshpande, Austin, TX (US);

Mark A. Banse, Austin, TX (US);

John E. Larson, Round Rock, TX (US);

Fernando A. Morales, Austin, TX (US);

Thang Q. Nguyen, Austin, TX (US);

Inventors:

Sanjay R. Deshpande, Austin, TX (US);

Mark A. Banse, Austin, TX (US);

John E. Larson, Round Rock, TX (US);

Fernando A. Morales, Austin, TX (US);

Thang Q. Nguyen, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/00 (2006.01); G06F 13/36 (2006.01); G06F 13/40 (2006.01); G06F 13/16 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4022 (2013.01); G06F 13/1621 (2013.01);
Abstract

Ordered write transactions from requester devices to multiple target devices are controlled using switch point networks. The requester device and the multiple target devices for the write transactions are coupled to a network of interconnected switch points. Write requests are generated for a plurality of parcels associated with a block of data to be written. The write requests have a particular order associated with an order in which the parcels are to be written, and these write requests are provided to the switch point interconnection network in the particular order. At least one of the switch points is then used to control the flow of write requests to the multiple target devices such that the particular order is maintained. In one embodiment, the target devices are memory devices, and the particular order is based upon the AXI (Advanced eXtensible Interface) protocol.


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