The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Nov. 19, 2015
Applicant:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Inventors:

Jiezhi Chen, Kanagawa, JP;

Kuniharu Takahashi, Kanagawa, JP;

Hiroyuki Nagashima, Kanagawa, JP;

Yuichiro Mitani, Kanagawa, JP;

Katsuki Matsudera, Kanagawa, JP;

Kazunori Kanebako, Kanagawa, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01); G06F 11/10 (2006.01); G11C 11/56 (2006.01); G11C 29/52 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 16/04 (2006.01); G11C 29/02 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G06F 11/1072 (2013.01); G11C 11/5642 (2013.01); G11C 16/26 (2013.01); G11C 16/3418 (2013.01); G11C 29/52 (2013.01); G11C 16/0483 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 2029/0411 (2013.01);
Abstract

According to an embodiment, a semiconductor device includes an error corrector, a read controller, and a majority processor. The error corrector is configured to perform error correction on data read from a storage, and output the number of errors contained in the data when errors cannot be corrected by the error correction. The read controller is configured to read pieces of data from a first address in the storage according to respective read conditions, select, from the read conditions, a read condition corresponding to a smallest of the numbers of errors obtained by the error correction performed on the pieces of data corresponding to the respective read conditions, and perform reading from the first address multiple times according to the selected read condition. The majority processor is configured to perform a majority process between a plurality of pieces of data obtained by the multiple times of reading.


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