The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 30, 2017
Filed:
Sep. 26, 2015
Intel Corporation, Santa Clara, CA (US);
Debendra Das Sharma, Saratoga, CA (US);
Michelle C. Jen, Sunnyvale, CA (US);
Joseph Murray, Scottsdale, AZ (US);
INTEL CORPORATION, Santa Clara, CA (US);
Abstract
A low-latency internode messaging scheme bypasses the nodes' I/O stacks to use fabrics or links that support memory process logic (e.g., SMI) or electrical process logic (e.g., PCIe) on the 'node side' between the nodes and a pooled memory controller (or pooled storage controller), and on the 'pooled side' between that controller and its pooled memory or storage. The controller may translate and redirect messages and look up addresses. The approaches accommodate 2-level memory (locally attached node memory and accessible pooled memory) with either or both levels private, globally shared, allocated to a subset of the nodes, or any combination. Compatible interrupt schema use the messaging links and components.