The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 30, 2017

Filed:

Sep. 04, 2015
Applicants:

Heung Kyu Kwon, Seongnam-si, KR;

Hae Gu Lee, Asan-si, KR;

Byeong Yeon Cho, Suwon-si, KR;

Inventors:

Heung Kyu Kwon, Seongnam-si, KR;

Hae Gu Lee, Asan-si, KR;

Byeong Yeon Cho, Suwon-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); G06F 1/16 (2006.01); H01L 23/498 (2006.01); H01L 23/544 (2006.01); H01L 23/00 (2006.01); H01L 25/10 (2006.01); H01L 25/00 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01); H05K 1/02 (2006.01); H05K 3/34 (2006.01);
U.S. Cl.
CPC ...
G06F 1/1601 (2013.01); G06F 1/16 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 23/544 (2013.01); H01L 24/97 (2013.01); H01L 25/105 (2013.01); H01L 25/50 (2013.01); H01L 21/561 (2013.01); H01L 23/3128 (2013.01); H01L 24/16 (2013.01); H01L 2223/54406 (2013.01); H01L 2223/54426 (2013.01); H01L 2223/54433 (2013.01); H01L 2223/54486 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/97 (2013.01); H01L 2225/1023 (2013.01); H01L 2225/1058 (2013.01); H01L 2924/14 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/15321 (2013.01); H01L 2924/15331 (2013.01); H01L 2924/1815 (2013.01); H01L 2924/18161 (2013.01); H05K 1/0269 (2013.01); H05K 3/3436 (2013.01); H05K 2201/10159 (2013.01); H05K 2201/10515 (2013.01); H05K 2201/10734 (2013.01); H05K 2201/10977 (2013.01);
Abstract

A semiconductor package includes a printed circuit board (PCB), a chip bonded to the PCB, a mold protecting the chip and exposing a backside surface of the chip, via openings extending in the mold to expose first contacts bonded to the PCB, and at least one first marking inscribed in a marking region of the mold between the backside surface of the chip and the vias. The mold has an exposed molded underfill (eMUF) structure covering the sides of the chip while exposing the backside surface of the chip. A PoP package includes a top package stacked on and electrically connected to the semiconductor package.


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