The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Dec. 17, 2015
Applicant:

Vanguard International Semiconductor Corporation, Hsinchu, TW;

Inventors:

Chih-Wei Lin, Jhubei, TW;

Pi-Kuang Chuang, Taichung, TW;

Chao-Wei Wu, Changhua, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/266 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/266 (2013.01); H01L 21/823418 (2013.01); H01L 27/088 (2013.01); H01L 29/0649 (2013.01); H01L 29/1095 (2013.01); H01L 29/66681 (2013.01);
Abstract

A high-voltage semiconductor device is provided. The device includes a semiconductor substrate including a well region of a first conductivity type and an isolation structure in the well region. First and second regions are respectively defined on both sides of the isolation structure. First and second gate structures are respectively disposed on the first and second regions. First and second implant regions of a second conductivity type that is different from the first conductivity type are respectively in the first and second regions and adjacent to the isolation structure. A counter implant region is in the well region under the isolation structure and laterally extends under the first and second implant regions. The counter implant region has the first conductivity type and has a doping concentration that is greater than that of the well region. A method for fabricating the high-voltage semiconductor device is also disclosed.


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