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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9660069 B1

PDFFull Text
Date of Patent:
May. 23, 2017

Filed:

Apr. 20, 2016

Group iii nitride integration with cmos technology

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Can Bayram, Champaign, IL (US);

Christopher Peter D'Emic, Ossining, NY (US);

William J. Gallagher, Ardsley, NY (US);

Effendi Leobandung, Stormville, NY (US);

Devendra K. Sadana, Pleasantville, NY (US);

Assignee:

International Business Machines Corporation, Armonk, NY (US);

Attorneys:

Scully, Scott, Murphy & Presser, P.C.

Louis J. Percello, Esq.

Primary Examiner:

George Fourson, III

Int. Cl.
CPC ...
H01L 21/8258 (2006.01); H01L 29/778 (2006.01); H01L 27/06 (2006.01); H01L 29/20 (2006.01); H01L 29/16 (2006.01); H01L 29/04 (2006.01); H01L 29/06 (2006.01); H01L 21/8252 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); H01L 21/31 (2006.01); H01L 21/3205 (2006.01); H01L 21/768 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H01L 21/84 (2006.01); H01L 29/66 (2006.01); H01L 23/535 (2006.01); H01L 29/205 (2006.01); H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 21/0254 (2013.01); H01L 21/02381 (2013.01); H01L 21/02433 (2013.01); H01L 21/02645 (2013.01); H01L 21/30604 (2013.01); H01L 21/31 (2013.01); H01L 21/3205 (2013.01); H01L 21/768 (2013.01); H01L 21/8252 (2013.01); H01L 21/8258 (2013.01); H01L 21/823807 (2013.01); H01L 21/823871 (2013.01); H01L 21/823878 (2013.01); H01L 21/84 (2013.01); H01L 23/535 (2013.01); H01L 27/06 (2013.01); H01L 27/0617 (2013.01); H01L 27/092 (2013.01); H01L 27/1207 (2013.01); H01L 29/04 (2013.01); H01L 29/045 (2013.01); H01L 29/06 (2013.01); H01L 29/0642 (2013.01); H01L 29/0649 (2013.01); H01L 29/16 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66462 (2013.01); H01L 21/02389 (2013.01); H01L 21/2015 (2013.01); H01L 29/7786 (2013.01);
Abstract

A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the substrate includes a topmost silicon layer and a <111> silicon layer located beneath the topmost silicon layer. Next, a trench is formed within the Group III nitride device region to expose a sub-surface of the <111> silicon layer. The trench is then partially filled with a Group III nitride base material, wherein the Group III nitride material base material has a topmost surface that is coplanar with, or below, a topmost surface of the topmost silicon layer.

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