The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Apr. 09, 2015
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Ching-Yun Chang, Yunlin County, TW;

Chi-Mao Hsu, Tainan, TW;

Wei-Ming Hsiao, Miaoli County, TW;

Nien-Ting Ho, Tainan, TW;

Kuo-Chih Lai, Tainan, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/092 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0922 (2013.01); H01L 21/28088 (2013.01); H01L 21/82345 (2013.01); H01L 29/4966 (2013.01);
Abstract

A semiconductor process of forming metal gates with different threshold voltages includes the following steps. A substrate having a first area and a second area is provided. A dielectric layer and a first work function layer are sequentially formed on the substrate of the first area and the second area. A second work function layer is directly formed on the first work function layer of the first area. A third work function layer is directly formed on the first work function layer of the second area, where the third work function layer is different from the second work function layer. The present invention also provides a semiconductor structure formed by said semiconductor process.


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