The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 2017
Filed:
Apr. 27, 2015
Applicant:
Stmicroelectronics International N.v., Schiphol, NL;
Inventors:
Vikas Rana, Noida, IN;
Amit Chhabra, Delhi, IN;
Assignee:
STMICROELECTRONICS INTERNATIONAL N.V., Schiphol, NL;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 17/693 (2006.01); H01L 27/092 (2006.01); H01L 27/12 (2006.01); H03K 17/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/092 (2013.01); H01L 27/1203 (2013.01); H03K 17/693 (2013.01); H03K 17/005 (2013.01); H03K 2217/0018 (2013.01);
Abstract
An integrated circuit die includes a plurality of transistors formed in a semiconductor substrate, the body regions of the transistors on a doped well region of the semiconductor substrate. A body bias voltage generator generates a positive body bias voltage, and a negative body bias voltage in the ground body bias voltage. A multiplexer selectively outputs one of the positive, negative, or ground body bias voltage to the doped well region of the semiconductor substrate based on the temperature of the semiconductor substrate.