The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Apr. 15, 2015
Applicant:

Gan Systems Inc., Ottawa, CA;

Inventors:

Greg P. Klowak, Ottawa, CA;

Ahmad Mizan, Kanata, CA;

John Roberts, Kanata, CA;

Assignee:

GaN Systems Inc., Ottawa, CA;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/15 (2006.01); H01L 31/02 (2006.01); H01L 29/78 (2006.01); H01L 23/498 (2006.01); H01L 23/482 (2006.01); H01L 29/20 (2006.01); H01L 23/522 (2006.01); H01L 23/532 (2006.01); H01L 23/31 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49844 (2013.01); H01L 23/4824 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 29/2003 (2013.01); H01L 29/78 (2013.01); H01L 23/3107 (2013.01); H01L 29/778 (2013.01); H01L 2224/18 (2013.01);
Abstract

Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.


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