The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Mar. 23, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Hyun-Kook Park, Anyang-si, KR;

Yeong-Taek Lee, Seoul, KR;

Dae-Seok Byeon, Seongnam-si, KR;

Yong-Kyu Lee, Hwaseong-si, KR;

Hyo-Jin Kwon, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 13/00 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0069 (2013.01); G11C 11/1675 (2013.01); G11C 11/1693 (2013.01); G11C 13/0002 (2013.01); G11C 13/0023 (2013.01); G11C 13/0061 (2013.01); G11C 13/0064 (2013.01); G11C 13/0097 (2013.01); G11C 2213/71 (2013.01);
Abstract

A method of writing data in a resistive memory device having a memory cell array divided into first and second tiles includes; performing a first simultaneous write operation by performing a set write operation performed on resistive memory cells of the first tile while simultaneously performing a reset write operation on resistive memory cells of the second tile in response to the write command, and performing a second simultaneous write operation by performing a reset write operation on resistive memory cells of the first tile while simultaneously performing a set write operation on resistive memory cells of the second tile in response to the write command.


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