The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 23, 2017

Filed:

Oct. 19, 2009
Applicants:

Karthikeyan Vaithianathan, Beaverton, OR (US);

Arvind Sudarsanam, Logan, UT (US);

Inventors:

Karthikeyan Vaithianathan, Beaverton, OR (US);

Arvind Sudarsanam, Logan, UT (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 7/50 (2006.01); G06F 7/544 (2006.01); G06F 17/10 (2006.01); G06F 7/508 (2006.01); G06F 7/505 (2006.01);
U.S. Cl.
CPC ...
G06F 7/544 (2013.01); G06F 17/10 (2013.01); G06F 7/505 (2013.01); G06F 7/508 (2013.01); G06F 2207/5442 (2013.01);
Abstract

Embodiments of a near optimal configurable adder tree for arbitrary shaped 2D block sum of absolute differences (SAD) calculation engine are generally described herein. Other embodiments may be described and claimed. In some embodiments, a configurable two-dimensional adder tree architecture for computing a sum of absolute differences (SAD) for various block sizes up to 16 by 16 comprises a first stage of one-dimensional adder trees and a second stage of one-dimensional adder trees, wherein each one-dimensional adder tree comprises an input routing network, a plurality of adder units, and an output routing network.


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