The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Sep. 10, 2014
Applicant:

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Inventors:

Yasushi Niimura, Matsumoto, JP;

Toshiaki Sakata, Matsumoto, JP;

Assignee:

FUJI ELECTRIC CO., LTD., Kawasaki-Shi, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/36 (2006.01); H01L 29/739 (2006.01); H01L 21/266 (2006.01); H01L 29/66 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 21/266 (2013.01); H01L 29/0634 (2013.01); H01L 29/0696 (2013.01); H01L 29/0878 (2013.01); H01L 29/0886 (2013.01); H01L 29/1095 (2013.01); H01L 29/36 (2013.01); H01L 29/66348 (2013.01); H01L 29/66712 (2013.01); H01L 29/7395 (2013.01); H01L 29/7827 (2013.01);
Abstract

An ndrift layer is a parallel pn layer having an n-type region and a p-type region are alternately arranged in the direction parallel to the main surface so as to come into contact with each other, and have a width in a direction parallel to the main surface of the substrate which is less than a length in a direction perpendicular to the main surface of the substrate. A second-main-surface-side lower end portion of the p-type region has a structure in which a high-concentration lower end portion and a low-concentration lower end portion of a p-type low-concentration region are repeated at a predetermined pitch in the direction parallel to the main surface of the substrate. It is possible to provide a super junction MOS semiconductor device which can improve a trade-off relationship between turn-off loss and turn-off dv/dt and improve avalanche resistance.


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