The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Sep. 10, 2014
Applicants:

Furukawa Electric Co., Ltd., Tokyo, JP;

Fuji Electric Co., Ltd., Kawasaki-shi, JP;

Inventors:

Kazuyuki Umeno, Tokyo, JP;

Tatsuyuki Shinagawa, Tokyo, JP;

Keishi Takaki, Tokyo, JP;

Ryosuke Tamura, Tokyo, JP;

Shinya Ootomo, Tokyo, JP;

Assignees:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 21/02 (2006.01); H01L 21/66 (2006.01); H01L 29/20 (2006.01); H01L 29/201 (2006.01); H01L 29/205 (2006.01); H01L 29/66 (2006.01); H01L 29/861 (2006.01); H01L 29/15 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7787 (2013.01); H01L 21/0254 (2013.01); H01L 21/0262 (2013.01); H01L 21/02458 (2013.01); H01L 22/12 (2013.01); H01L 29/155 (2013.01); H01L 29/201 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01); H01L 29/66431 (2013.01); H01L 29/861 (2013.01);
Abstract

A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 μm.


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