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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9653552 B1

PDFFull Text
Date of Patent:
May. 16, 2017

Filed:

Jul. 08, 2016

Body-tied, strained-channel multi-gate device and methods

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Hong-Nien Lin, Taichung, TW;

Horng-Chih Lin, Hsin-chu, TW;

Tiao-Yuan Huang, Cupertino, CA (US);

Assignee:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Attorney:

Slater Matsil, LLP

Primary Examiner:

David S Blum

Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2012.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 29/16 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 21/8238 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1054 (2013.01); H01L 21/823807 (2013.01); H01L 21/823821 (2013.01); H01L 27/0886 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/1608 (2013.01); H01L 29/66795 (2013.01); H01L 29/7842 (2013.01); H01L 29/7849 (2013.01); H01L 29/7851 (2013.01); H01L 29/78687 (2013.01);
Abstract

A fin-FET or other multi-gate transistor is disclosed. The transistor comprises a semiconductor substrate having a first lattice constant, and a semiconductor fin extending from the semiconductor substrate. The fin has a second lattice constant, different from the first lattice constant, and a top surface and two opposed side surfaces. The transistor also includes a gate dielectric covering at least a portion of the top surface and the two opposed side surfaces, and a gate electrode covering at least a portion of the gate dielectric. The resulting channel has a strain induced therein by the lattice mismatch between the fin and the substrate. This strain can be tuned by selection of the respective materials.

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