The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Jan. 03, 2014
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Peng Cheng, Greensboro, NC (US);

James S. Dunn, Jericho, VT (US);

Blaine J. Gross, Essex Junction, VT (US);

Qizhi Liu, Lexington, MA (US);

James A. Slinkman, Montpelier, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 29/45 (2006.01); H01L 21/308 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/3081 (2013.01); H01L 27/0207 (2013.01); H01L 27/1207 (2013.01); H01L 29/0649 (2013.01); H01L 29/165 (2013.01); H01L 29/456 (2013.01); H01L 29/66477 (2013.01); H01L 29/78 (2013.01); H01L 29/7842 (2013.01); H01L 27/088 (2013.01);
Abstract

Various embodiments include field effect transistors (FETs) and methods of forming such FETs. One method includes: forming a first set of openings in a precursor structure having: a silicon substrate having a crystal direction, the silicon substrate substantially abutted by a first oxide; a silicon germanium (SiGe) layer overlying the silicon substrate; a silicon layer overlying the SiGe layer; a second oxide overlying the silicon layer; and a sacrificial layer overlying the second oxide, wherein the first set of openings each expose the silicon substrate; undercut etching the silicon substrate in a direction perpendicular to the crystal direction of the silicon substrate to form a trench corresponding with each of the first set of openings; passivating exposed surfaces of at least one of the SiGe layer or the silicon layer in the first set of openings; and at least partially filling each trench with a dielectric.


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