The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Mar. 15, 2016
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Damon Holmes, Scottsdale, AZ (US);

David Burdeaux, Tempe, AZ (US);

Partha Chakraborty, Tempe, AZ (US);

Ibrahim Khalil, Munich, DE;

Hernan Rueda, Chandler, AZ (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 23/552 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 23/66 (2006.01); H01L 27/02 (2006.01); H01L 21/8234 (2006.01); H01L 21/3205 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/552 (2013.01); H01L 21/32051 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 21/823475 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/66 (2013.01); H01L 27/0203 (2013.01); H01L 2223/6644 (2013.01);
Abstract

A transistor includes a semiconductor substrate having an intrinsic active device, a first terminal, and a second terminal. The transistor also includes an interconnect structure formed of multiple layers of dielectric material and electrically conductive material on an upper surface of the semiconductor substrate. The interconnect structure includes a pillar, a tap interconnect, and a shield structure formed from the electrically conductive material. The pillar electrically contacts the first terminal, extends through the dielectric material, and connects to a first runner. The tap interconnect electrically contacts the second terminal, extends through the dielectric material, and connects to a second runner. The shield structure extends from a shield runner through the dielectric material toward the semiconductor substrate. The shield structure is positioned between the pillar and the tap interconnect to limit feedback capacitance between the tap interconnect and the pillar.


Find Patent Forward Citations

Loading…