The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Jul. 31, 2015
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;

Inventors:

Chia-Ming Pan, Tainan, TW;

Chiang-Ming Chuang, Hemei Township, Changhua County, TW;

Pei-Chi Ho, Xingang Township, Chiayi County, TW;

Ping-Pang Hsieh, Tainan, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/28 (2006.01); H01L 29/788 (2006.01); H01L 29/66 (2006.01); H01L 29/423 (2006.01); H01L 27/11521 (2017.01);
U.S. Cl.
CPC ...
H01L 21/28273 (2013.01); H01L 27/11521 (2013.01); H01L 29/42328 (2013.01); H01L 29/66553 (2013.01); H01L 29/66825 (2013.01); H01L 29/788 (2013.01);
Abstract

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate and a floating gate structure formed over the substrate. The semiconductor structure further includes a dielectric structure formed over the floating gate structure and a control gate structure formed over the dielectric structure. The semiconductor structure further includes a first spacer formed over a lower portion of a sidewall of the control gate structure and an upper spacer formed over an upper portion of the sidewall of the control gate structure. In addition, a portion of the control gate structure is in direct contact with the upper spacer.


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