The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Feb. 18, 2016
Applicant:

Piecemakers Technology, Inc., Hsinchu, TW;

Inventors:

Tah-Kang Joseph Ting, Taipei, TW;

Gyh-Bin Wang, Hsinchu County, TW;

Ming-Hung Wang, Hsinchu, TW;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); G11C 11/4093 (2006.01); G11C 11/4076 (2006.01); G11C 11/4094 (2006.01); G11C 11/4096 (2006.01);
U.S. Cl.
CPC ...
G11C 11/4093 (2013.01); G11C 11/4076 (2013.01); G11C 11/4094 (2013.01); G11C 11/4096 (2013.01);
Abstract

A memory device includes a common data bus, a plurality of memory banks and a control circuit. The memory banks are coupled to the common data bus. The memory banks share the common data bus. Each of the memory banks includes a storage device and a data register. The data register is coupled between the storage device the common data bus, and is arranged for storing data read from the storage device. The control circuit is coupled to storage devices and data registers of the memory banks, and is arranged for referring to an address signal and an access signal to control the storage device of said each memory bank to output the data to the corresponding data register, and referring to the address signal and a programmable latency time to control the data registers to output data from the memory banks to the common data bus.


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