The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Jan. 08, 2013
Applicants:

Freescale Semiconductor, Inc., Austin, TX (US);

Michael Priel, Netanya, IL;

Eliya Babitsky, Caesaria, IL;

Asher Berkovitz, Kiryat Ono, IL;

Vladimir Nusimovich, Hertzelia, IL;

Inventors:

Michael Priel, Netanya, IL;

Eliya Babitsky, Caesaria, IL;

Asher Berkovitz, Kiryat-Ono, IL;

Vladimir Nusimovich, Hertzelia, IL;

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
G06F 17/505 (2013.01); G06F 17/5045 (2013.01);
Abstract

A method of performing logic synthesis of at least a part of an integrated circuit design. The method comprises identifying a first and at least one further module within the IC design that are mutually exclusive, selecting at least one register element within the first identified module and at least one register element within the at least one further identified module to be shared, and merging the first and at least one further mutually exclusive modules such that at least one common register element is shared between the first and at least one further mutually exclusive modules for the register elements selected to be shared.


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