The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 16, 2017
Filed:
Dec. 30, 2015
Arteris, Inc., Campbell, CA (US);
David A. Kruckemyer, San Jose, CA (US);
Craig Stephen Forrest, San Francisco, CA (US);
ARTERIS, Inc., Campbell, CA (US);
Abstract
Compression of address bits within a cache coherent subsystem of a chip is performed, enabling a cache coherent subsystem to avoid transmitting, storing, and operating upon unnecessary address information. Compression is performed according to any appropriate lossless algorithm, such as discarding of bits or code book lookup. The algorithm may be chosen according to constraints on logic delay and silicon area. An algorithm for minimum area would use a number of bits equal to the rounded up binary logarithm of the sum of all addresses of all memory regions. A configuration tool generates a logic description of the compression algorithm. The algorithm may be chosen automatically by the configuration tool. Decompression may be performed on addresses exiting the coherent subsystem.