The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 2017

Filed:

Oct. 01, 2011
Applicants:

Blaise Fanning, Folsom, CA (US);

Anil K. Sabbavarapu, Austin, TX (US);

Inventors:

Blaise Fanning, Folsom, CA (US);

Anil K. Sabbavarapu, Austin, TX (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/445 (2006.01); G06F 11/14 (2006.01);
U.S. Cl.
CPC ...
G06F 9/44505 (2013.01); G06F 11/1441 (2013.01); Y02B 60/185 (2013.01);
Abstract

The setting in a configuration register is controlled based on a value stored in a management register and/or based on generation of a reset signal during a debugging operation or detection of a malfunction or power state transition in an electronic system. The management register may allocate a single bit to each configuration register, and the setting to be loaded into the configuration register is to be controlled based on the value of the bit. Additionally, or alternatively, the setting in the configuration register may be controlled when the reset signal assumes a value indicating that a default setting is to be stored.


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