The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Oct. 31, 2013
Applicant:

Floadia Corporation, Kodaira-shi, Tokyo, JP;

Inventors:

Yasuhiro Taniguchi, Kodaira, JP;

Kosuke Okuyama, Kodaira, JP;

Assignee:

FLOADIA CORPORATION, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/108 (2006.01); H01L 29/94 (2006.01); H01L 27/11521 (2017.01); H01L 29/788 (2006.01); H01L 27/11 (2006.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); H01L 27/11558 (2017.01); G11C 16/04 (2006.01); G11C 14/00 (2006.01); H01L 27/1156 (2017.01); H01L 29/36 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); G11C 14/0063 (2013.01); G11C 16/0441 (2013.01); H01L 27/1104 (2013.01); H01L 27/1116 (2013.01); H01L 27/1156 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11558 (2013.01); H01L 29/36 (2013.01); H01L 29/788 (2013.01); H01L 29/7881 (2013.01);
Abstract

To propose a non-volatile semiconductor memory device capable of injecting charge into a floating gate by source side injection even in a single-layer gate structure. In a non-volatile semiconductor memory device (), while each of the memory transistor (MGA) and the switch transistor (SGA) is made to have a single-layer gate structure, when a selected memory cell () is turned on by applying a high voltage to one end of a memory transistor (MGA) from a source line (SL) during data programming and applying a low voltage to one end of the switch transistor (SGA) from a bit line (BL), a voltage drop occurs in a low-concentration impurity extension region (ET) in the memory transistor (MGA) between the source line (SL) and the bit line (BL) to generate an intense electric field, and charge can be injected into the floating gate (FG) by source side injection using the intense electric field.


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