The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Jan. 24, 2015
Applicant:

Semitronix Corporation, Hangzhou, CN;

Inventors:

Xu Ouyang, Hangzhou, CN;

Yongjun Zheng, Hangzhou, CN;

Zheng Shi, Hangzhou, CN;

Peiyong Zhang, Hangzhou, CN;

Assignee:

Semitronix Corporation, Hangzhou, CN;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
H01L 22/32 (2013.01); G01R 31/2884 (2013.01); H01L 22/14 (2013.01); H01L 22/34 (2013.01);
Abstract

A programmable test chip includes a target chip to be tested and addressing circuits fabricated on the same wafer. The addressing circuits can be placed in the scribe lines or a pre-allocated area of the wafer. When testing the target chip, a circuit connecting the target chip and the addressing circuits can be fabricated on demand. In some cases the target chip is not connected to the addressing circuits, and a DUT array exists in a scribe line having a connecting circuit prefabricated between the addressing circuits with the DUT array for testing the DUT array in the scribe line. When the need for testing the target chip arises, the prefabricated connecting circuit can be cut, and the connecting circuit connecting the target chip and the addressing circuits can be fabricated. Based on results from such test chips, the manufacturing process can be better studied.


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