The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Mar. 18, 2016
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Gary E. Dickerson, Gloucester, MA (US);

Seng (victor) Keong Lim, Fremont, CA (US);

Samer Banna, San Jose, CA (US);

Gregory Kirk, Pleasanton, CA (US);

Mehdi Vaez-Iravani, Los Gatos, CA (US);

Assignee:

APPLIED MATERIALS, INC., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/67 (2006.01); H01L 21/66 (2006.01); H01L 21/324 (2006.01); H01L 21/027 (2006.01); H01L 21/683 (2006.01);
U.S. Cl.
CPC ...
H01L 22/12 (2013.01); H01L 21/0273 (2013.01); H01L 21/324 (2013.01); H01L 21/67115 (2013.01); H01L 21/67248 (2013.01); H01L 21/67253 (2013.01); H01L 21/6831 (2013.01);
Abstract

Embodiments of the present disclosure relate to an apparatus and a method for reducing the adverse effects of exposing portions of an integrated circuit (IC) device to various forms of radiation during one or more operations found within the IC formation processing sequence by controlling the environment surrounding and temperature of an IC device during one or more parts of the IC formation processing sequence. The provided energy may include the delivery of radiation to a surface of a formed or a partially formed IC device during a deposition, etching, inspection or post-processing process operation. In some embodiments of the disclosure, the temperature of the substrate on which the IC device is formed is controlled to a temperature that is below room temperature (e.g., <20° C.) during the one or more parts of the IC formation processing sequence.


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