The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Jan. 21, 2016
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chun-Wei Yu, Tainan, TW;

Hsu Ting, Tainan, TW;

Chueh-Yang Liu, Tainan, TW;

Yu-Ren Wang, Tainan, TW;

Kuang-Hsiu Chen, Tainan, TW;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/033 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 29/08 (2006.01); H01L 29/24 (2006.01); H01L 29/267 (2006.01); H01L 29/161 (2006.01); H01L 29/165 (2006.01); H01L 29/78 (2006.01); H01L 23/535 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823814 (2013.01); H01L 21/02065 (2013.01); H01L 21/28123 (2013.01); H01L 23/535 (2013.01); H01L 29/0847 (2013.01); H01L 29/161 (2013.01); H01L 29/165 (2013.01); H01L 29/24 (2013.01); H01L 29/267 (2013.01); H01L 29/7848 (2013.01);
Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a first gate structure on the substrate and a first spacer adjacent to the first gate structure; forming a first epitaxial layer in the substrate adjacent to the first gate structure; forming a first hard mask layer on the first gate structure; removing part of the first hard mask layer to form a protective layer on the first epitaxial layer; and removing the remaining first hard mask layer.


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