The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Dec. 24, 2014
Applicant:

Tokyo Electron Limited, Tokyo, JP;

Inventors:

Akinobu Kakimoto, Nirasaki, JP;

Youichirou Chiba, Nirasaki, JP;

Takumi Yamada, Nirasaki, JP;

Daisuke Suzuki, Nirasaki, JP;

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/285 (2006.01); C30B 1/02 (2006.01); C30B 29/06 (2006.01); H01L 21/67 (2006.01); H01L 21/02 (2006.01); C30B 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76877 (2013.01); C30B 1/023 (2013.01); C30B 29/06 (2013.01); H01L 21/28525 (2013.01); H01L 21/28531 (2013.01); H01L 21/67109 (2013.01); H01L 21/76879 (2013.01); C30B 25/00 (2013.01); H01L 21/02667 (2013.01);
Abstract

A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate includes: forming an impurity-doped first semiconductor layer along a wall surface which defines the depression; forming, on the first semiconductor layer, a second semiconductor layer which is lower in impurity concentration than the first semiconductor layer and which is smaller in thickness than the first semiconductor layer; annealing the workpiece to form an epitaxial region at the bottom of the depression corresponding to crystals of the semiconductor substrate from the first semiconductor layer and the second semiconductor layer; and etching the first amorphous semiconductor region and the second amorphous semiconductor region.


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