The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Feb. 16, 2015
Applicant:

Freescale Semiconductor, Inc., Austin, TX (US);

Inventors:

Chris N. Stoll, Dripping Springs, TX (US);

Chris P. Nappi, Austin, TX (US);

George R. Redford, Tempe, AZ (US);

Jayson D. Vogler, Austin, TX (US);

Khurram Waheed, Austin, TX (US);

Assignee:

NXP USA, Inc., Austin, TX (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G01R 31/317 (2006.01);
U.S. Cl.
CPC ...
G06F 13/4068 (2013.01); G01R 31/31707 (2013.01); G01R 31/31727 (2013.01);
Abstract

An integrated circuit includes a substrate, a master system on the substrate, a slave system on the substrate that is coupled to communicate with the master system, a first clock signal coupled to the master system, and a second clock signal coupled to the slave system. The master system is configured to isolate the slave system from the master system while a first test of the master system is conducted in parallel with a second test of the slave system. The master system uses the first clock signal during the first test and the slave system uses the second clock signal during the second test.


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