The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 2017

Filed:

Jan. 10, 2014
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Abha Jain, Noida, IN;

Hitesh Mohan Kumar, Greater Noida, IN;

Parag Choudhary, Toronto, CA;

Viren Agarwal, Kalimpong, IN;

Assignee:

Cadence Design Systems, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/048 (2013.01); G06F 3/0484 (2013.01);
U.S. Cl.
CPC ...
G06F 3/0484 (2013.01);
Abstract

The present disclosure relates to a computer-implemented method for electronic design simulation. The method may include receiving, using at least one processor, an electronic design and displaying, at a graphical user interface, at least a portion of the electronic design. Embodiments may also include allowing a user to select at least one design variable at the graphical user interface. Embodiments may also include simulating the electronic design, based upon, at least in part, the selected at least one design variable and in response to the simulation, automatically displaying an updated value at the graphical user interface.


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