The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Jun. 30, 2016
Applicant:

Intel Ip Corporation, Santa Clara, CA (US);

Inventors:

Georgios Yorgos Palaskas, Portland, OR (US);

Paolo Madoglio, Beaverton, OR (US);

Peter Preyler, Weyer, AT;

Rotem Banin, Pardes-hana, IL;

Assignee:

Intel IP Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03M 1/66 (2006.01); H03M 1/06 (2006.01); H03M 7/42 (2006.01); H03M 1/46 (2006.01);
U.S. Cl.
CPC ...
H03M 1/06 (2013.01); H03M 1/466 (2013.01); H03M 7/42 (2013.01);
Abstract

A digital to time converter (DTC). The DTC includes a lookup table, a divider, a thermometric array and a switched capacitor array. The lookup table is configured to generate one or more corrections based on thermometric bits of an input signal. The divider is configured to generate a plurality of divider signals from an oscillator signal based on the one or more corrections. The thermometric array is configured to generate a medium approximation signal from the plurality of divider signals based on the one or more corrections. The switched capacitor array is configured to generate a digital delay signal from the medium approximation signal based on the one or more corrections and switched capacitor bits of the input signal.


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