The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 2017

Filed:

Feb. 06, 2015
Applicant:

Mitsubishi Electric Corporation, Chiyoda-ku, JP;

Inventors:

Kenji Hamada, Tokyo, JP;

Naruhisa Miura, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/15 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01); H01L 29/16 (2006.01); H01L 21/265 (2006.01); H01L 29/32 (2006.01); H01L 21/04 (2006.01); H01L 27/06 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/063 (2013.01); H01L 21/046 (2013.01); H01L 21/26506 (2013.01); H01L 27/0664 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/32 (2013.01); H01L 29/66068 (2013.01); H01L 29/7395 (2013.01); H01L 29/7397 (2013.01); H01L 29/0834 (2013.01);
Abstract

An IGBT includes an emitter electrode, base regions, an emitter region, a collector region, a collector electrode, a gate insulating film provided in contact with the silicon carbide semiconductor region, the emitter region, and the base region, and a gate electrode that faces the gate insulating film. A FWD includes a base contact region provided adjacent to the emitter region and electrically connected to the emitter electrode, and a cathode region disposed in the upper layer part on the other main surface side of the silicon carbide semiconductor region, provided adjacent to the collector region, and electrically connected to the collector electrode. The IGBT further includes a reduced carrier-trap region disposed in a principal current-carrying region of the silicon carbide semiconductor region located above the collector region and having a smaller number of carrier traps than the silicon carbide semiconductor region located above the cathode region.


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